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FEATURES Active Voltage Positioning with Gain and Offset Adjustment Optimal Compensation for Superior Load Transient Response Fixed 1.5 V, 1.8 V and 2.5 V Output Versions Dual N-Channel Synchronous Driver On-Board Linear Regulator Controller Total Output Accuracy 1% Over Temperature High Efficiency, Current-Mode Operation Short Circuit Protection Overvoltage Protection Crowbar Protects Loads with No Additional External Components Power Good Output SO-16 Package APPLICATIONS Desktop Computer Supplies ACPI-Compliant Power Systems General Purpose DC-DC Converters GENERAL DESCRIPTION
Dual Power Supply Controller for Desktop Systems ADP3156
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE-
DELAY NONOVERLAP DRIVE VREF +15% 2R CROWBAR IN OFF CMPI S R gm VREF REFERENCE VLDO 1.20V FB OFF-TIME CONTROL VIN SENSE- R VT1 VREF +5% VREF -5%
SD
Q
VT2
CT
CMPT
ADP3156
The ADP3156 is a highly efficient synchronous buck switching regulator controller optimized for converting the 3.3 V or 5 V main supply into lower supply voltages required on the motherboards of Pentium(R) III and other high performance processor systems. The ADP3156 uses a current mode, constant off-time architecture to drive two external N-channel MOSFETs at a programmable switching frequency that can be optimized for size and efficiency. It also uses a unique supplemental regulation technique called active voltage positioning to enhance load transient performance. Active voltage positioning results in a DC/DC converter that provides the best possible transient response using the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard currentmode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3156 provides accurate and reliable short circuit protection and adjustable current limiting. It also includes an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 15%.
CMP
The ADP3156 contains a linear regulator controller that is designed to drive an external N-channel MOSFET. This linear regulator is used to generate the auxiliary voltages (AGP, GTL, etc.) required in most motherboard designs, and has been designed to provide a high bandwidth load-transient response. A pair of external feedback resistors sets the linear regulator output voltage.
VCC +12V VIN +5V CIN +
22 F R1
1F SD VCC DRIVE1 VLDO
L
VO2 35k 1000 F 20k R2 CCOMP 200pF
RSENSE VO +
ADP3156
FB CMP SENSE- CT AGND PGND SENSE+ 1nF
CO
DRIVE2
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation. All other trademarks are the property of their respective holders.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3156-SPECIFICATIONS (0 C
Parameter OUTPUT ACCURACY ADP3156-1.5 V ADP3156-1.8 V ADP3156-2.5 V OUTPUT VOLTAGE LINE REGULATION INPUT DC SUPPLY CURRENT2 Normal Mode Shutdown CURRENT SENSE THRESHOLD VOLTAGE CT PIN DISCHARGE CURRENT Symbol VO
TA
+70 C, VCC = 12 V, VIN = 5 V, unless otherwise noted)1
Conditions Min 1.480 1.777 2.475 ILOAD = 10 A (Figure 2) VIN = 4.75 V to 5.25 V VSD = 0.6 V TA = +25C, VSD = 2.0 V VSENSE- Forced to VOUT - 3% TA = +25C VOUT in Regulation VOUT = 0 V CT = 150 pF CL = 7000 pF (DRIVE1, 2) TA = +25C % Above Output Voltage % Below Output Voltage -8 1.8 125 Typ 1.500 1.800 2.500 0.05 4.1 140 145 65 2 2.45 120 5 -5 500 % Above Output Voltage 9 15 275 2.2 VSENSE- Forced to VOUT + 3% VSENSE- Forced to VOUT - 3% CMP = Open 0.8 2.4 500 0.35 Figure 2, VLDOIN = 1.8 V RPROG = 5 k, R2 = 20 k, IO2 = 1 A Part Active Part in Shutdown 1.47 1.5 1 1.53 24 5.5 250 165 Max 1.520 1.823 2.525 Units V V V % mA A mV A A s ns % % s % k mmho V V kHz A V
VO
IQ
VSENSE(TH) IT
10 3.2 200 8
OFF-TIME DRIVER OUTPUT TRANSITION TIME POSITIVE POWER GOOD TRIP POINT3 NEGATIVE POWER GOOD TRIP POINT3 POWER GOOD RESPONSE TIME CROWBAR TRIP POINT ERROR AMPLIFIER OUTPUT IMPEDANCE ERROR AMPLIFIER TRANSCONDUCTANCE ERROR AMPLIFIER MINIMUM OUTPUT VOLTAGE ERROR AMPLIFIER MAXIMUM OUTPUT VOLTAGE ERROR AMPLIFIER BANDWIDTH -3 dB LINEAR REGULATOR FEEDBACK CURRENT LINEAR REGULATOR OUTPUT VOLTAGE SHUTDOWN (SD) PIN Low Threshold High Threshold Input Current
tOFF t R , tF VPWRGD VPWRGD tPWRGD VCROWBAR ROERR gm(ERR) VCMPMIN VCMPMAX BWERR IFB VO2
SDL SDH SDIC
0.6 2.0 10
V V A
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Specifications subject to change without notice. 2 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs. 3 The trip point is for the output voltage coming into regulation. Specifications subject to change without notice.
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PIN FUNCTION DESCRIPTIONS
Pin 1, 2, 15 3 4 5 6 7 8 9 10 11 12 13 14 16
Mnemonic NC AGND SD FB VLDO SENSE- SENSE+ CT CMP PWRGD VCC DRIVE2 DRIVE1 PGND
Function No Connect. Analog Ground. All internal signals of the ADP3156 are referenced to this ground. Shutdown. A logic high will place the ADP3156 in shutdown and disable both outputs. This pin is internally pulled down. Feedback connection for the linear controller. Connect this pin to the resistor divider network to set the output voltage of the linear regulator. Gate Drive for the linear regulator N-channel MOSFET. Connects to the internal resistor divider that senses the output voltage. This pin is also the reference input for the current comparator. (+) input for the current comparator. The output current is sensed as a voltage at this pin with respect to SENSE-. External Capacitor CT connection to ground sets the off-time of the device. Error Amplifier output and compensation point. The voltage at this output programs the output current control level between the SENSE pins. Power Good. An open drain signal indicates the output voltage is within a 5% regulation band. Supply Voltage to ADP3156. Gate Drive for the (bottom) Synchronous Rectifier N-channel MOSFET. The voltage at DRIVE2 swings from ground to VCC. Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to VCC. Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate capacitances to this pin. PGND should have a low impedance path to the source of the synchronous MOSFET.
PIN CONFIGURATION 16-Lead SOIC
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . . . -0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . -0.3 V to +16 V Operating Ambient Temperature Range . . . . . . 0C to +70C Junction Temperature Range . . . . . . . . . . . . . . 0C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
NC 1 NC 2 AGND 3 SD 4
16 15 14
PGND NC DRIVE1
DRIVE2 TOP VIEW FB 5 (Not to Scale) 12 VCC
13 11 10 9
ADP3156
VLDO 6
PWRGD CMP CT
ORDERING GUIDE
SENSE- 7
Model ADP3156JR-1.5 ADP3156JR-1.8 ADP3156JR-2.5
Buck Converter Output Voltage 1.5 V 1.8 V 2.5 V
Package Option R-16A/SO-16 R-16A/SO-16 R-16A/SO-16
SENSE+ 8
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3156 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3156
22 100k ESR = 34m 2700 F 2 (10V) 22 F 1F 1F L2 1.7 H 5V 5V RTN 12V RTN 12V
ADP3156-1.8
P SYSTEM
1 2 3 4 5
NC NC AGND SD FB VLDO SENSE- SENSE+
PGND 16 NC 15 DRIVE1 14 DRIVE2 13 VCC 12 PWRGD 11 CMP 10 CT 9 CT 200pF R2 16k CCOMP 2nF R1 110k IRL3103 IRL3103
L1 3H
RSENSE 12.9m
ESR = 60m 470 F 4
VO 1.8V 7A
10BQ015 RTN
IRL3103
2k
6
47pF
7 8
VO2 +1.5V 4A 1000 F RTN
R4 5k R3 20k
220 1nF 220
Figure 2. ADP3156 Typical VRM8.4 AGP and GTL Chipset DC/DC Converter Circuit
VCC DRIVE1 DRIVE2 PGND
AGND
PWRGD
SENSE+ SENSE-
DELAY NONOVERLAP DRIVE VREF +15% 2R CROWBAR IN OFF CMPI S R gm VREF REFERENCE VLDO FB OFF-TIME CONTROL VIN SENSE- R VT1 VREF +5% VREF -5%
SD
Q
VT2
CT
CMPT
ADP3156
CMP
Figure 3. Functional Block Diagram
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Typical Performance Characteristics-ADP3156
100
450 400 SUPPLY CURRENT - mA
45 40 35 30 25 QGATE(TOTAL) = 100nC 20 15 10 5 0 45 58 83 134 OPERATING FREQUENCY - kHz 397
95
EFFICIENCY - %
VOUT = 2.5V VOUT = 1.8V
FREQUENCY - kHz
350 300 250 200 150 100 50
90
85 VOUT = 1.5V 80 SEE FIGURE 2 75 0.5 1.5 2.5 3.5 4.5 5.5 OUTPUT CURRENT - Amps 6.5
0 50
100 200 300 400 500 600 700 800 TIMING CAPACITOR - pF
Figure 4. Efficiency vs. Output Current
Figure 5. Frequency vs. Timing Capacitor
Figure 6. Supply Current vs. Operating Frequency
SEE FIGURE 2 IOUT = 10A PRIMARY N-DRIVE DRIVER OUTPUT
1
SEE FIGURE 2
VCC = +12V VIN = +5V I OUT = 10A
OUTPUT VOLTAGE 50mV/DIV
SECONDARY N-DRIVE DRIVER OUTPUT
2
OUTPUT CURRENT 7A TO 1A
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
100ns/DIV
10 s/DIV
Figure 7. Gate Switching Waveforms
Figure 8. Driver Transition Waveforms
Figure 9. Transient Response, 7 A-1 A of Figure 2 Circuit
OUTPUT VOLTAGE 50mV/DIV
VCC VOLTAGE 5V/DIV
3
OUTPUT CURRENT 1A TO 7A
REGULATOR OUTPUT VOLTAGE 1V/DIV
4
10 s/DIV
10ms/DIV
Figure 10. Transient Response, 1 A-7 A of Figure 2 Circuit
Figure 11. Power-On Start-Up Waveforms
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ADP3156
12V SD CMP 1k CT 4700pF AGND PGND VOUT
ADP3156
VCC 1F 0.1 F
DRIVE1 DRIVE2 SENSE+ SENSE-
100k 1.2V
OP27
0.1 F
Figure 12. Closed-Loop Test Circuit for Accuracy
THEORY OF OPERATION
The ADP3156 uses a current-mode, constant-off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous buck topology. Constant off-time operation offers several performance advantages, including that no slope compensation is required for stable operation. A unique feature of the constant-off-time control technique is that since the off-time is fixed, the converter's switching frequency is a function of the ratio of input voltage to output voltage. The fixed off-time is programmed by the value of an external capacitor connected to the CT pin. The on-time varies in such a way that a regulated output voltage is maintained as described below in the cycle-bycycle operation. Under fixed operating conditions the on-time does not vary, and it varies only slightly as a function of load. This means that switching frequency is fairly constant in standard VRM applications. In order to maintain a ripple current in the inductor, which is independent of the output voltage (which also helps control losses and simplify the inductor design), the off-time is made proportional to the value of the output voltage. Normally, the output voltage is constant and therefore the offtime is constant as well.
Active Voltage Positioning
monitors the voltage between the SENSE+ and SENSE- pins. When the voltage level between the two pins reaches the threshold level VT1, the high side drive output is switched to ground, which turns off the high side MOSFET. The timing capacitor CT is then discharged at a rate determined by the off-time controller. While the timing capacitor is discharging, the low side drive output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has discharged to the threshold voltage level VT2, comparator CMPT resets the SR flip-flop. The output of the flip-flop forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold VT1, thus tracking the load current. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high.
Power Good
The ADP3156 has an internal monitor that senses the output voltage and drives the PWRGD pin of the device. This pin is an open drain output whose high level (when connected to a pullup resistor) indicates that the output voltage has been within a 5% regulation band of the targeted value for more than 500 s. The PWRGD pin will go low if the output is outside the regulation band for more than 500 s.
Output Crowbar
The output voltage is sensed at the SENSE- pin. SENSE- is connected to an internal voltage divider. The output of the divider is then compared to the internal reference. A unique supplemental regulation technique called active voltage positioning with optimal compensation adjusts the output voltage as a function of the load current so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning, sometimes recommended for use with other architectures, has poor dynamic performance which renders it ineffective under the stringent repetitive transient conditions specified in Intel VRM documents. Consequently, such techniques do not allow the minimum possible number of output capacitors to be used. Optimally compensated active voltage positioning, as used in the ADP3156, provides a bandwidth for transient response that is limited only by parasitic output inductance. This yields an optimal load transient response with the minimum number of output capacitors.
Cycle-by-Cycle Operation
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 15% greater than the targeted value, the ADP3156 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 2.0 V, but is pulled up to 2.3 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than 1.0 V, the crowbar will release, allowing the output voltage to recover to 2.0 V if the fault condition has been removed.
Shutdown
The ADP3156 has a shutdown (SD) pin that is pulled down by an internal resistor. In this condition the device functions normally. This pin should be pulled high to disable the output drives.
APPLICATION INFORMATION
During normal operation (when the output voltage is regulated), the voltage-error amplifier and the current comparator (CMPI) are the main control elements. (See the block diagram of Figure 3). During the on-time of the high side MOSFET, CMPI -6-
A number of power conversion requirements must be considered when designing an ACPI compliant system. In normal operating mode, 12 V, 5 V and 3.3 V are available from the main supply. These voltages need to be converted into the appropriate supply voltages for the Northbridge core, the Southbridge core and RAMBUS memory, as well as supplies for GTL and I/O drivers, CMOS memory and clock and graphics (AGP) circuits.
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During the standby operating state, the 12 V, 5 V and 3.3 V power supply outputs are disabled, and only a low power 5 V rail (5VSB) is available. The circuits that must remain active in standby must be able to run from 5VSB. To accomplish this, power routing is required to allow switching between normal and standby supplies. Lack of a 12 V rail in standby makes control of linear outputs difficult, and with up to 8 A demand from the 1.5 V and 1.8 V rails, an all-linear solution is inefficient. Figure 13 shows a typical ACP-compliant Pentium III / chipset power management system using the ADP3155 and ADP3156. The ADP3155 provides VID switched output and two linear regulators for standby operation. A charge-pump-doubled 5VSB is ORed into the supply rail to supply the linear regulators during standby operation. The VID output collapses when the main 5 V rail collapses, but the N-channel MOSFET linear regulators can continue to supply current from the ~9 V supply. The ADP3156 provides 1.8 V via its main switching regulator, and allows efficient linear regulation of 1.5 V rail by using the 1.8 V output as its source. The design parameters for an ACPI-compliant Pentium III peripheral system depend on what peripherals are used (e.g., AGP) and what their specifications are. The following is an example where the higher of two low system voltages (1.8 V and 1.5 V) is created directly with the main buck converter, and also used to supply power for the lower output voltage using the ADP3156's linear regulator controller. Input voltage (power source): VIN = 5 V Auxiliary voltage: VCC = 12 V Output voltages and tolerances: V1 = 1.8 V 5%, V2 = 1.5 V 5% Maximum output currents: I1MAX = 3 A, I2MAX = 4 A Slew rate of load current change: di1/dt = di2 /dt >10 A/s The absence of an inductor on the 1.5 V linear regulated output allows the output current to respond quickly and the linear regulator MOSFET's resistance to be modulated quickly. This, and some small bypassing capacitors, essentially insulates the 1.5 V output from transient activity on the 1.8 V output. However, this same fast response characteristic means that any 1.5 V transient activity will be passed straight through the linear regulator to the 1.8 V output. This means that the 1.8 V output filter capacitor selection must consider both 1.8 V and 1.5 V load transients. In this design example, worst case consideration requires that the 1.8 V output be designed for transient current loading of I1MAX + I2MAX = 7 A. Also, because a practical switching regulator design will have a current slew rate of <1 A/s due to the inductor, nearly the entire 7 A transient current must be absorbed by the output capacitors.
CT Selection for Operating Frequency
The ADP3156 uses a constant-off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 3.3 V. During the off-time, CT is discharged by a constant current of 65 A. Once CT reaches 2.3 V, a new on-time cycle is initiated. The value of the off-time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency of fNOM = 200 kHz at an output voltage of 1.8 V, the corresponding off-time is:
V 1 tOFF = 1 - O = 3.2 s VIN f NOM
The timing capacitor can be calculated from the equation:
CT =
tOFF x 65 A 1V
= 208 pF
ATX (OR NLX) POWER SUPPLY
12V 5V 3.3V
12V 5V 3.3V 5V_PM ATX_POWERGOOD ATX_SHUTDOWN ATX_POWER GOOD 12V VCC ATXPG POWER MANAGEMENT STATE COMMAND 5V_PM PMSC 5V_PM
12V
5V_ALWAYS ATX_PGOOD ATX_SHUTDOWN GND
POWER MANAGEMENT FUNCTIONS
VCC
DUAL OUTPUT SUPPLY
ADP3156
LIN_ CTRLS 5V
ADP3155
LIN#2_ CTRLS 5V LIN#1_ CTRLS
VCC VID_4:0 MAIN_ CTRLS IN VID
TRIPLE OUTPUT SUPPLY
MAIN_ CTRLS IN
1.8V FOR SB CORE, MEM, ETC
OUT
SWITCHER
SWITCHER
CTRLS
CTRLS
OUT
CPU VCORE @ VID
1.5V VTT FOR GTL
OUT
LINEAR
IN CTRLS
5V_PM
IN
LINEAR#1
CTRLS
OUT
3.3V_PM FOR POWER MANAGEMENT
1.5V OR 3.3V VDDQ FOR AGP TYPEDET# FOR AGP SELECT
VDDQ SELECT
3.3V_IN 1.5V_IN
3.3V
5V_PM
IN
POWER ROUTING
LINEAR#2
CTRLS
OUT
2.5V_PM FOR CMOS, CLOCK, MEMORY
Figure 13. ACPI-Compliant Pentium III System Block Diagram
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The converter operates at the nominal operating frequency only at the VOUT specified above, and at light load. At higher load conditions, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VOUT = 1.8 V is calculated from Equation 1, and is a function of the finite resistances of various components in the power converter.
COUT Selection--Determining the ESR
lowest cost core is made of powdered iron, for example the #52 material from Micrometals, Inc., but yields a larger size inductor.
COUT Selection--Determining the Capacitance
The required ESR and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage stay below the values defined in the specification of the supplied circuitry. The capacitance must be large enough that the output is held up while the inductor current ramps up or down to the value corresponding to the new load current. Taking into account the 1% setpoint accuracy of the ADP3156, and assuming a 1% (or 15 mV) peak-to-peak ripple, the allowed static voltage deviation of the output voltage when the load changes between the minimum and maximum values is: (2 x 5% x 1.5 V) - (2 x 1% x 1.5 V) - (1% x 1.5 V) = 105 mV This sets the maximum ESR at 105 mV/7 A = 15 m. Four parallel capacitors of 470 F with a maximum ESR of 60 m will achieve the 15 m maximum net ESR. Whether or not the capacitance is sufficient must be determined after the inductor is selected.
Inductor Selection
The minimum capacitance of the output capacitor is determined from the requirement that the output be held up while the inductor current ramps up (or down) to the new value. The minimum capacitance should produce an initial dv/dt which is equal (but opposite in sign) to the dv/dt obtained by multiplying the di/dt in the inductor and the ESR of the capacitor.
C MIN = C MIN = IOMAX - IOMIN RE (di / dt ) 15 m 1.8 V / 3.36 H 7 A-0 A
(
)
= 871 F
In the above equation the value of di/dt is calculated as the smaller voltage across the inductor (i.e., the smaller of VIN - VOUT and VOUT) divided by the maximum inductance (3.36 H) of the inductor. The four parallel-connected 470 F capacitors have a total capacitance of 1880 F, so the minimum capacitance requirement is met with ample margin.
RSENSE
The minimum inductor value can be calculated from ESR, offtime, dc output voltage and allowed peak-to-peak ripple voltage using the following equation: L MIN1 = VOtOFF RE ( MAX ) 1.5 x 3.2 s x 7 m = = 2.24 H VRIPPLE p - p 15 mV
The value of RSENSE is based on the required output current. The current comparator of the ADP3156 has a threshold range that extends from 0 mV to 125 mV (minimum). Note that the full 125 mV range cannot be used for the maximum specified nominal current, as headroom is needed for current ripple and transients. The current comparator threshold sets the peak of the inductor current yielding a maximum output current IOMAX, which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE and allowing a 20% margin for overhead, and using the minimum current sense threshold of 125 mV yields: RSENSE = (125 mV)/[1.2(IOMAX + IRPP/2)] = 12.9 m Once RSENSE has been chosen, the peak short-circuit current ISC(PK) can be predicted from the following equation: ISC(PK) = (145 mV)/RSENSE = (145 mV)/(12.9 m)= 11.2 A The actual short-circuit current is less than the above-calculated ISC(PK) value because the off-time rapidly increases when the output voltage drops below 1 V. The relationship between the off-time and the output voltage is:
The minimum inductance gives a peak-to-peak ripple current of 2.14 A, or 35% of the maximum dc output current IOMAX. The inductor peak current in normal operation is: ILPEAK = IOMAX + IRPP/2 = 8.07 A The inductor valley current is: ILVALLEY = ILPEAK - IRPP /2 = 5.93 A The inductor for this application should have an inductance of not less than 2.24 H at full load current and should not saturate at the worst-case overload or short circuit current at the maximum specified ambient temperature. For this example, it is assumed the inductance might drop as much as 33% due to load current, so its initial value might be as high as 3.36 H.
Tips for Selecting the Inductor Core
tOFF
CT x 1 V VO + 2 A 360 k
Ferrite designs have very low core loss, so the design should focus on copper loss and on preventing saturation. Molypermalloy, or MPP, is a low loss core material for toroids, and it yields the smallest size inductor, but MPP cores are more expensive than ferrite cores or the Kool M(R) cores from Magnetics, Inc. The
With a short circuit across the output, the off-time will be about 104 s. During that time the inductor current gradually decays. The amount of decay depends on the L/R time constant in the output circuit. With an inductance of 2.24 H and total resistance of 40 m (the inductor's series resistance plus the sense resistor), the time constant will be 56 s. This yields a valley
f MIN =
1 tOFF
x
VIN - I IN RIN - IOMAX ( RDS(ON )HSF + RSENSE + RL ) - VO VIN - I IN RIN - IOMAX ( RDS(ON )HSF + RSENSE + RL - RDS(ON )LSF ) -8- (1)
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current of 1.7 A and an average short-circuit current of about 6.5 A--meaning that there is actually a small degree of shortcircuit current foldback. To safely carry the maximum current, the sense resistor must have a power rating of at least (11.2 A - 1.07 A)2 x 12.9 mW = 1.3 W.
Current Transformer Option
An alternative to using a low value and high power current sense resistor is to reduce the sensed current by using a low cost current transformer and a diode. The current can then be sensed with a small size, low cost SMT resistor. Using a transformer with one primary and 50 secondary turns reduces the worst-case resistor dissipation to a few mW. Another advantage of using this option is the separation of the current and voltage sensing, which makes the voltage sensing more accurate.
Power MOSFETs
economical choice for both the high side and low side positions. Those devices have an RDS(ON) of 14 m at VGS = 10 V and at +25C. The low side FET is turned on with at least 10 V. The high side FET, however, is turned on with only 12 V - 5 V = 7 V. Checking the typical output characteristics of the device in the data sheet, shows that for an output current of 10 A, and at a VGS of 7 V, the VDS is 0.15 V. This gives an RDS(ON) only slightly above the one specified at a VGS of 10 V, so the resistance increase due to the reduced gate drive can be neglected. The specified RDS(ON) at the expected highest FET junction temperature of +140C must be modified by an RDS(ON) multiplier, using the graph in the data sheet. In this case: RDS(ON)MULT = 1.7 Using this multiplier, the expected RDS(ON) at +140C is 1.7 x 14 = 24 m. The high side FET dissipation is: PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQGfMIN/IG ~ 2.54 W where the second term represents the turn-off loss of the FET. (In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate current. From the data sheet, QG is about 50 nC-70 nC and the gate drive current provided by the ADP3156 is about 1 A.) The low side FET dissipation is: PDFETLS = Irmsls2RDS(ON) = 0.49 W (Note that there are no switching losses in the low side FET.) To maintain an acceptable MOSFET junction temperature, proper heat sinking should be used. The heat sink and airflow are chosen based on how low the impedance must be reduced in order to keep the MOSFET's junction temperature at an acceptably low level, according to the formula: HA = [(TJMAXOP - TA)PDFET] - JC - CH where HA is the thermal resistance from the heat sink to ambient air (and depends on airflow), TJMAXOP is the user-determined maximum acceptable operating temperature of the MOSFET, and the last two factors are the thermal resistance from junction-to-case of the device, and case-to-heat sink. Typically, the junction-to-case thermal resistance is 2C/W, and the case-to-heat sink resistance is 0.5C/W.
CIN Selection and Input Current di/dt Reduction
Two external N-channel power MOSFETs must be selected for use with the ADP3156, one for the main switch, and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage VGS(TH) and the on resistance RDS(ON). The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum of VCC should be used. The maximum output current IOMAX determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3156 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT = 1.8 V, the maximum duty ratio of the high side FET is: DMAXHF = (1 - fMIN x tOFF) = (1 - 150 kHz x 3.2 s) = 52% The duty ratio of the low side (synchronous rectifier) FET under the maximum load condition is: DMAXLF = 1 - DMAXHF = 48% The maximum rms current of the high side FET is: IRMSHS = [DMAXHF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3]0.5 = 7.32 A rms The maximum rms current of the low side FET is: IRMSLS = [DMAXLF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3] = 7.03 A rms
0.5
The RDS(ON) for each FET can be derived from the allowable dissipation. Allowing 8% of the maximum output power for FET dissipation, the total dissipation will be: PFETALL = 0.08 VOIOMAX = 1.0 W Allocating half of the total dissipation for the high side FET and half for the low side FET, the required minimum FET resistances will be: RDS(ON)HSF(MIN) = 1 W x 52%/(7.32A)2 = 9.7 m RDS(ON)LSF(MIN) = 1 W x 48%/(7.03A)2 = 9.7 m Note that there is a trade-off between converter efficiency and cost. Larger FETs reduce the conduction losses and allow higher efficiency, but increase the system cost. If efficiency is not a major concern, the International Rectifier IRL3103 is an REV. 0 -9-
In continuous-inductor-current mode, the source current of the high side MOSFET is a square wave with a duty ratio of VO/VlN. To keep the input ripple voltage at a low value, one or more capacitors with low equivalent series resistance (ESR) and adequate ripple-current rating must be connected across the input terminals. The maximum rms current of the input bypass capacitors is: ICINRMS = IOMAX [DMAX x (1-DMAX)]0.5 = 3.5 A For an FA-type capacitor with 2700 mF capacitance and 10 V voltage rating, the ESR is 34 m and the allowed ripple current at 100 kHz (and similar frequencies) is 1.94 A. At +105C, two such capacitors may be connected in parallel to handle the calculated ripple current. To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/s, an additional small inductor should be inserted between the converter and the supply bus (see Figure 2).
ADP3156
Feedback Loop Compensation Design for Active Voltage Positioning
Optimized compensation of the ADP3156 allows the best possible containment of the peak-to-peak output voltage deviation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors, and this will produce an output voltage deviation equal to the ESR of the output capacitor array times the load current change. To correctly implement active voltage positioning, the low frequency output impedance (i.e., the output resistance) of the converter should be made equal to the maximum ESR of the output capacitor array. This can be achieved by having a single pole roll-off of the voltage gain of the gm error amplifier, where the pole frequency coincides with the ESR zero of the output capacitor. A gain with single pole roll-off requires that the gm amplifier output pin be terminated by the parallel combination of a resistor and capacitor. The required resistor value can be calculated from the equation:
calculated using Equation 2, where VOUT(OS) is the offset from the nominal VID-programmed value to the center of the specified regulation window for the output voltage. (Note this may be either positive or negative.) For clarification, that offset is given by:
1 VOUT (OS ) = (VHI +VLO )-VID 2
Finally, the compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor:
CCOMP =
CO x ESR RtTOTAL
Trade-Offs Between DC Load Regulation and AC Load Regulation
RC =
where:
275 k x RtTOTAL 275 k - RtTOTAL
16.4 k x RCS x IOMAX VHI -VLO
RtTOTAL =
where the quantities 16.4 k and 275 k are characteristics of the ADP3156, the value of the current sense resistor, RCS, has already been determined as above, and where VHI and VLO are the respective upper and lower limits allowed for regulation. Although a single termination resistor equal to RC would yield the proper voltage positioning gain, the dc biasing of that resistor would determine how the regulation band is centered (i.e., note that sometimes the specified regulation band is asymmetrical with respect to the nominal VID voltage.) With the ADP3156, the offset is already considered as part of the design procedure-- no special provision is required. To accomplish the dc biasing, it is simplest to use two resistors to terminate the gm output, with the lower resistor tied to ground and the upper resistor to the 12 V supply of the IC. The values of these resistors can be calculated using:
Casual observation of the circuit operation--e.g., with a voltmeter--would make it appear that the dc load regulation appears to be rather poor compared to a conventional regulator. This would be especially noticeable under very light or very heavy loads where the voltage is "positioned" near one of the extremes of the regulation window rather than near the nominal center value. It must be noted and understood that this low gain characteristic (i.e., loose dc load regulation) is inherently required to allow improved transient containment (i.e., to achieve tighter ac load regulation). That is, the dc load regulation is intentionally sacrificed (but kept within specification) in order to minimize the number of capacitors required to contain the load transients produced by the CPU.
Linear Regulator
RUPPER = RC x
and:
VDIV VOS
The ADP3156 linear regulator provides a low cost, convenient and versatile solution for generating a lower supply rail in addition to the main output. The maximum output load current is determined by the size and thermal impedance of the external N-channel power MOSFET that is controlled by the ADP3156. The output voltage, VO2 in Figure 14, is sensed at the FB pin of the ADP3156 and compared to an internal 1.2 V reference in a negative feedback loop which keeps the output voltage in regulation. If the load is being reduced or increased, the FET drive will also be reduced or increased by the ADP3156 to provide a well regulated 1% accurate output voltage. The output voltage is programmed by adjusting the value of the external resistor RPROG, shown in Figure 14.
VIN = +1.8V
ADP3156
RLOWER = RC x
VOS VDIV - VOS
VO2 = +1.5V IO2 = 4.0A
VLDO IRL3103 FB RPROG 5k 20k
1000 F/10V
where VDIV is the resistor divider supply voltage (e.g., the recommended 12 V), and VOS is the offset voltage required on the amplifier to produce the desired offset at the output. VOS is
Figure 14. Linear Regulator Configuration
VOS =
RC RtTOTAL
Rt Rt x 0.8 V + VOUT (OS ) TOTAL - 1.7 V TOTAL + 6 RCS IOMAX 1.36 k 275 k
(2)
-10-
REV. 0
ADP3156
Efficiency of the Linear Regulator LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The efficiency and corresponding power dissipation of the linear regulator are not determined by the ADP3156. Rather, these are a function of input and output voltage and load current. Efficiency is approximated by the formula: = 100% x (VOUT VIN) The corresponding power dissipation in the MOSFET, together with any resistance added in series from input to output is given by: PLDO = (VIN(LDO) - VOUT(LDO)) x IOUT(LDO) Minimum power dissipation and maximum efficiency are accomplished by choosing the lowest available input voltage that exceeds the desired output voltage. However, if the chosen input source is itself generated by a linear regulator, its power dissipation will be increased in proportion to the additional current it must now provide. For most PC systems, the lowest available input source for the linear regulators, which is not itself generated by a linear regulator, is 3.3 V from the main power supply. However, in this case, the main output of the ADP3156 creates a lower voltage that may be used as the source supply for the linear regulator. Assuming that a 1.8 V main output is used to provide power for a 1.5 V linear regulator output, the efficiency will nominally be 1.5 V / 1.8 V = 83%. If the 1.5 V output must supply a 4 A maximum load (a total of 6 W), the steady state dissipation in the MOSFET may be as high as: PLDO(MAX) = (VIN - VOUT) = 1.2 W
The following guidelines are recommended for optimal performance of a switching regulator in a PC system:
General Recommendations
1. For best results, a four-layer (minimum) PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. Each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. 2. Whenever high currents must be routed between PCB layers vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. The power and ground planes should overlap each other as little as possible. It is generally the easiest (although not necessary) to have the power and signal ground planes on the same PCB layer. The planes should be connected nearest to the first input capacitor where the input ground current flows from the converter back to the power source (e.g., 5 V). 4. If critical signal lines (including the voltage and current sense lines of the ADP3156) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. 5. The PGND pin of the ADP3156 should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the power ground plane using the shortest possible trace. However, the power ground plane should not extend under other signal components, including the ADP3156 itself. If necessary, follow the preceding guideline to use the signal plane as a shield between the power ground plane and the signal circuitry. 6. The AGND pin of the ADP3156 should connect first to the timing capacitor (on the CT pin), and then into the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used--the compensation capacitor being the next most critical. 7. The output capacitors of the power converter should be connected to the signal ground plan even though power current flows in the ground of these capacitors. For this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane in between the input and output capacitors. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). 8. The output capacitors should also be connected as closely as possible to the load (or connector) which receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors also should be distributed, and generally in proportion to where the load tends to be more dynamic.
x
IOUT(MAX) = (1.8 V - 1.5 V) x 4 A
The minimum acceptable on resistance of the MOSFET that would deliver the 4 A load with only a 0.3 V difference between input and output is: RDS(ON, MAX) = (VOUT - VIN) / IOUT(MAX) = (1.8 V - 1.5 V) / 4 A = 75 m There are many MOSFETs to choose from that can support the maximum power dissipation without need for a heat sink and without exceeding the calculated maximum on-resistance. For simplicity it may be desirable to use the same MOSFET as is used for the main power converter. The output voltage may be programmed by the RPROG resistor as follows: V 1.5 RPROG = O2 - 1 x 20 k = - 1 x 20 k = 5 k 1.2 1.2 V The output filter capacitor maximum allowed ESR is: ESR~VTR2/IOMAX = 0.036/0.5 = 0.072 where VTR2 is the maximum allowed transient deviation on the output. This requirement is met using a 1000 F/10 V LXV series capacitor from United Chemicon. For applications requiring higher output current, a heat sink and/or a larger MOSFET should be used to reduce the MOSFET's junction-to-ambient thermal impedance.
REV. 0
-11-
ADP3156
9. Absolutely avoid crossing any signal lines over the switching power path loop, described below.
Power Circuitry
10. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs, and the power Schottky diode if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause highenergy ringing, and it accommodates the high current demand with minimal voltage loss. 11. A power Schottky diode (1~2 Adc rating) placed from the lower FET's source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper FET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower FET turns off in advance of the upper FET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower FET, draws current through the inherent body-drain diode of the FET. The upper FET turns on, and the reverse recovery characteristic of the lower FET's body-drain diode prevents the drain voltage from being pulled high quickly. The upper FET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper FET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower FET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 12. A small ferrite bead inductor placed in series with the drain of the lower FET can also help to reduce this previously described source of switching power loss. 13. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias both directly on the mounting pad and immediately surrounding it is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance--especially if the vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 14. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors.
Signal Circuitry
16. The output voltage is sensed and regulated between the AGND pin (which connects to the signal ground plane) and the SENSE- pin. The output current is sensed (as a voltage) and regulated between the SENSE- pin and the SENSE+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the SENSE- trace should be routed atop the signal ground plane, and the SENSE+ and SENSE- traces should be routed as a closely coupled pair (SENSE+ should be over the signal ground plane as well). 17. The SENSE+ and SENSE- traces should be Kelvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desirable to both have the ADP3156 close to the output capacitor bank and not in the output power path so that any voltage drop between the output capacitors and the AGND pin is minimized, and voltage regulation is not compromised.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Standard Small Outline Package (SOIC) (R-16A)
0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80)
16 1 9 8
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
-12-
REV. 0
PRINTED IN U.S.A.
0.2440 (6.20) 0.2284 (5.80)
C3598-2-4/99
15. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor, and any snubbing elements that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines.

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